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Matching Circuits Can Be Small: Partial Evaluation and Reconfiguration for Flexible FPGA-based Packet Processing

Author: Hager, S., Bendyk, D. & Scheuermann, B.
Published in: Journal of Parallel and Distributed Computing, 109(C), 42-49
Year: 2017
Type: Academic articles
DOI: 10.1016/j.jpdc.2017.05.004

Network functions like routing or firewalling require specialized hardware such as FPGAs to process packets at high rates. Such hardware must be fast enough to process packets at line rate, and it must be programmable to update the installed packet processing policy. However, these goals are conflicting because a generic programmable circuit must provide sufficient resources to support a wide range of policies, which can lead to unused circuitry and low clock rates. Also, it misses logic optimization opportunities with regard to the structure of the installed policy. In this work, we investigate the optimization potential of policy-specific generated network processing circuits. Using the example of router forwarding information bases (FIBs), we demonstrate that FIB-specialized circuits need significantly fewer logic resources than equivalent generic forwarding circuits. In combination with the partial reconfiguration capability of FPGAs, we obtain efficient low-latency forwarding engines whose matching circuitry can be replaced on demand. We propose to specialize packet matching circuits on processing policies.The specialized circuits are logic optimized and therefore small.We evaluate this approach at the example of an IP forwarding circuit.We use partial reconfiguration to hot-swap specialized circuits at runtime.No device shutdown is required for a policy update.

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